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The present invention relates to a level shifter. More specifically, the present invention relates to a multi-level level shifter circuit having a single ended input.
Many integrated circuits or IC applications require translating one or more signals from one voltage level to another. Such circuits that perform this function are more commonly known as xe2x80x9clevel shiftersxe2x80x9d. A typical level shifter requires both an input signal and its complement to drive it. If the complement of the input signal isn""t provided, it may be generated using an inverter referenced to the input signal level; however, generating the compliment of the input signal may not be practical if the inverter power supply isn""t readily available.
Other known level shifter circuits require only a single-ended-input; however, such level shifters may draw DC current during operation thereon (when the input is high for example). This DC power dissipation may not be acceptable in certain applications.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
Features of the present invention may be found in a multi-level level shifter circuit having a single-ended input and adapted to translate one or more signals from one voltage level to another. More specifically, the present invention provides a level shifter that doesn""t draw DC current and doesn""t require a complementary input or an additional power supply if the complementary signal isn""t available. A multi-level level shifter means that, at least in one embodiment, the level shifter may operate over a wide input voltage range that includes levels between the power and ground rails. In other words, the input voltage level does not need to be rail-to-rail for the level shifter to operate properly. A single-ended input means that, in at least one embodiment, the compliment of the input signal isn""t required for proper circuit operation.
One embodiment of the present invention relates to a level shifter circuit having a single-ended input and at least three transistor devices. The first transistor device is coupled to at least the input and is adapted to have a threshold voltage less than 0V. The second transistor device is coupled to at least the first transistor device, while a level shifter transistor device is coupled to at least the first and second transistor devices.
Other embodiments of the present invention may comprise the level shifter circuit having a native NMOS transistor device adapted to have a negative threshold voltage (i.e., less than 0V) over all operating conditions. Furthermore, other embodiments may include at least one other NMOS transistor device and two or more PMOS transistor devices.
Yet another embodiment of the present invention relates to a multi-level level shifter circuit having a single ended input. This embodiment includes a first NMOS transistor device coupled to at least the input and adapted to have a threshold voltage less than 0V and a first PMOS transistor device coupled to at least the first NMOS device and an output. A second PMOS transistor device is coupled to at least the output and the first NMOS and first PMOS transistor devices, while a second NMOS transistor device is coupled to at least the output and the first NMOS and second PMOS transistor devices.
Still another embodiment of the present invention relates to an integrated circuit including a level shifter circuit having a single ended input. In this embodiment the level shifter circuit comprises at least three transistor devices. The first transistor device is coupled to at least the input and is adapted to have a threshold voltage less than 0V. The second transistor device is coupled to at least the first transistor device, while a level shifter transistor device is coupled to at least the first and second transistor devices.
One embodiment of the present invention relates to a method of shifting the voltage level of a single-ended input. If the input signal exceeds a first voltage threshold a low signal is output and if the input signal is below a second voltage threshold a high signal is output.
Another embodiment of the present invention relates to a method of translating the voltage level of a single-ended input signal. In this embodiment a first voltage level (a high signal for example) is output if the single ended input signal is in a first state (a high state for example). A second voltage level (a low signal for example) is output if the single ended input is in a second state (a low state for example). In another embodiment, it is contemplated that the first voltage level may comprise a low signal or the second voltage level may comprise a high signal.
Yet still another embodiment of the present invention relates to a method of translating the voltage of a single-ended input signal from one level to another. The method comprises determining if the input signal is greater than a threshold voltage. A low signal is output if the input signal is greater than the voltage threshold, while a high signal is output if the input signal is less than a second threshold value. Further, the method eliminates static current drain. It is contemplated that, in one embodiment, if the input signal is less than the first and greater than the second threshold value, the circuit may be in an undetermined state.